1. Field of the Invention
The present invention relates to a memory access apparatus. More particularly, the present invention relates to a memory access apparatus which executes an access process that complies with a memory access request issued by a processor in cooperation with a memory control circuit.
2. Description of the Related Art
According to one example of this type of apparatus, a plurality of requests respectively issued from a plurality of request sources are arbitrated by an arbiter. A memory access circuit writes desired data in an SDRAM when a writing request is approved by the arbiter. Moreover, the memory access circuit reads out the desired data from the SDRAM when a reading-out request is approved by the arbiter.
However, in the above-described apparatus, a delay occurs to a transfer operation of requests resulting from a quality of a signal line which links the request source and the arbiter, and this delay may sometimes prevent speeding-up of a memory access process.